Generate HDL in QSYS with DSP builder block fails

Altera_Forum · ‎08-03-2016

Hi

I am currently trying to generate HDL in the Qaurtus Prime QSYS version 15.1.0.189. I have succesfull imported the dspbuilder block by adding the path and connecting the DSP builder block in the hps_qsys system. But when I am trying the generate the HDL, the generator keeps giving me some errors which halts the process.

The errors are:

Error: invalid command name "quartus_synth_callback"while executing "quartus_synth_callback PfcCurReg_dut"

Info: PfcCurReg_dut_0: "hps_qsys" instantiated PfcCurReg_dut "PfcCurReg_dut_0"

Error: Generation stopped, 33 or more modules remaining

Info: hps_qsys: Done "hps_qsys" with 20 modules, 3 files

Error: qsys-generate failed with exit code 1: 2 Errors, 2 Warnings

Info: Finished: Create HDL design files for synthesis

Are am missing something crucial to the implemtation of the DSP builder block?

Please advice?

Best regards

Kim

Ghe0rghe · ‎10-01-2020

I too am having the same problem:

It seems like I can successfully import DSPBuilder-generated IP cores into Qsys using their hw.tcl file and .vhd files, but for some reason they do not compile in Qsys, where I receive the same error as you: "invalid command name "quartus_synth_callback""

Best,

-Gheorghe