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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Generate PCI Express using SOPC Builder

Altera_Forum
Honored Contributor II
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Hi,  

I am new at Altera, PCI Express, and Avalone MM, ST. If someone out there have done this before or knew something about it please help me. Thanks in advance. Here it is my problem: 

I followed chapter 8 of the PCI Express Compiler User Guide and able to generated, ran simulation and saw data written to and read from the onchip mem. So all that was all great, but how to take that and apply to what I want to do is an issue. Well first I want to understand what it does first maybe that would give me clues on how to implement my design. This is what I got 

 

BAR Size --> Avalon Address My Understanding 

1:0 4KB 80000000 - 80000FFF bar to interface wi onchip mem 

it matches with the mem size. Ok 

2 32KB 80000000 - 80007FFF what determines this bar to be  

32KB, I know this bar is used to interface DMA controller  

64B 80001000 - 8000103F Why 64B?, is it always the same or changes, what are dependencies? 

16K 80004000 - 80007FFF Why 16KB? the address ends at  

the same as the bar2. 

Another thing is on the Avalon Configuation Tab the is a table "Address 

Translation Table Size" this was set to 2 pages with each page has 1MB - 20 bit each. Why is that? I know I can read, I read but it was quite confusing hope someone could shine some light when I go back and read then it would make sense. 

 

I thinks if some experienced Altera person can help me to understand this I might be able to figure what to do with my design, which is that I have data coming from rx radio loaded into external ddr mem (for fifo) and sent to cpu via pci express, the same for the transmit path from cpu to tx radio. CPU also requires to program Tx, RX radio card via pcie, spi bus. Plus some general purpose communication... 

 

Thanks
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