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How can I make PCI compiler work well?

Altera_Forum
Honored Contributor II
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I use PCI 32-bit Host Bridge ip core in my project with sopc builder flow. After generating the sopc builder system, I put the PCI ip module in the top **.bdf file. Then I load the Altera’s constraint files and compile my design. Now I find that I can't transact data from or to the PCI. I don’t know where the problem is. Maybe there is something wrong with the sdc file. The error is attached. Could you help me please? 

In addition, clk_pci_compiler0 is connected to pll 33MHZ clock output.  

 

 

Warning: At least one of the filters had some problems and could not be matched. Warning: clk_pci_compiler0 could not be matched with a port or pin or register or keeper or net. Warning: Ignored assignment: create_clock -name {PCI_CLOCK} -period 30.000 -waveform { 0.000 15.000 } [get_ports {clk_pci_compiler0}] Warning: Argument <targets> gives an empty collection Warning: At least one of the filters had some problems and could not be matched. Warning: rstn_pci_compiler0 could not be matched with a port. Warning: At least one of the filters had some problems and could not be matched. Warning: PCI_CLOCK could not be matched with a clock. Warning: Ignored assignment: set_input_delay -add_delay -max -clock [get_clocks {PCI_CLOCK}] 0.000 [get_ports {rstn_pci_compiler0}] Warn
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