I’m using Qsys flow to implement a Avalon MM pcie interface. The interface I need is both a target and an initiator. The target functions are for the configuration registers of my IP code, just simple 32-bit registers. I only need one bar for that, so BAR0. I have also enable the Txs Memory mapped slave for my initiator functions. Both my Rxm_BAR0 and my Txs are exported to my design, that is not connected in the qsys framework I bolt my code into the interface up one level. Qsys thinks that because I didn’t connect my BAR0 inside the Qsys framework that I need a size zero bar. The only way I can get Qsys to allocate some bar space is to connect the bar0 to some slave interface inside qsys, but that does not help at all.Questions: How does one get space allocated in a BAR if that BAR is exported? thanks, joe
okay, so it turns out that you cannot export the Rxm_BAR0 (even though Qsys allows you to, grrrrrrrr). Qsys needs to see something bolted to the BAR interface before it will allow any allocation of BAR memory space. So if you just export the BAR, Qsys says meah, he does not need any space. You need to connect an Avalon-MM pipelined bridge to Rxm_BARn in Qsys. Then export the Avalon master side of the bridge.