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Hello,
As for the YCrCb 4:2:2 video format, what's mapping of the pixels on the port vid_data of the HDMI IP (two pixels per clock config)?
Should it be this mapping:
As for 10-bits color depth format, how can I receive this indication from the HDMI IP? What indication about the pixel color depth does the HDMI IP provide?
Thank you!
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Any response?
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Hi amildm,
Apologize for the delayed response.
>As for the YCrCb 4:2:2 video format, what's mapping of the pixels on the port vid_data of the HDMI IP (two pixels per clock config)?
>As for 10-bits color depth format, how can I receive this indication from the HDMI IP? What indication about the
>pixel color depth does the HDMI IP provide?
For YCbCr 4:2:2 input format , you may refer to Chapter 5.1.2. Source Video Resampler of the HDMI Intel® FPGA IP User Guide that shows a diagram on how the pixel data is mapped.
Below picture shows the YCbCr 4:2:2 color space pixel bit-field mappings per symbol, this is an example for YCbCr422 is transmitted using 24bpp (8 bpc) HDMI transport:
For Intel HDMI IP, the most significant bit (MSB) will be fill first with pixel data and the unused Least-significant bit (LSBs) are set to zero. The placement of Y and Cb/Cr data is as shown in above figure. For 10bpc case, the placement of Y and Cb/Cr will be the same.
You may refer below link for more information:
HDMI Intel® FPGA IP User Guide - 5.1.2. Source Video Resampler
Thank you for your patience.
Best Regards,
ZulsyafiqH_Intel
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I tried this mapping, but it did not work for me.
I used the following mapping and it worked for me (for YCrCb 422 decimation):
[47:32] - Cb/Cr[15:0]
[31:16] - Y[15:0]
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Hi amildm,
Good day.
I wish to follow up with you about this case.
Hoping to hear back from you so that we can proceed for next step.
Thank you.
Best Regards,
ZulsyafiqH_Intel
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I tried this mapping, but it did not work for me.
I used the following mapping and it worked for me (for YCrCb 422 decimation):
[47:32] - Cb/Cr[15:0]
[31:16] - Y[15:0]
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Hi amildm,
Good day.
Based on your latest response, you are actually using 16bpc, not 10 bpc.
For 10 bpc it should be as below:
Cb/Cr[47:38], Y[31:22], Cb/Cr[15:11] , Y[10:6].
For HDMI, it receive any color formats from the source which means need to set it from source side.
Basically for HDMI, there's a correlation between bpc setting and TMDS clock. Generally, sending higher bpc setting would mean TMDS clock runs faster.
You may refer to the link below for more information:
HDMI Intel® FPGA IP User Guide - 4.3.1.2. PLL Intel FPGA IP Cores
Thank you.
Best Regards,
ZulsyafiqH_Intel
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Hi amildm,
Good day.
I wish to follow up with you on this case. Do you still have further inquiries on this issue? I will remain this loop open for 2 days.
If we do not receive any response from you to the previous answer that I have provided.
This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.
Best Regards,
ZulsyafiqH_Intel
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Hi amildm,
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Thank you.
Best Regards,
ZulsyafiqH_Intel
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