I am working on a scaler box with C10 GX and would like to know how to config the HDMI IOPLL and fPLL.
I knew the reference design has values, e.g. HDMI_VIP..
But the reference is 297MHz, how could I find correct parameters for 4K60, 4K30....?
All the clocking conversion for different HDMI resolution is typically handled by the reconfig controller design algorithm of the HDMI example design.
Cyclone 10 GX only support 2 symbol for clock mode
There are 3 main clocks used by HDMI Ip example design.
- pixel clk = Total_Horizontal_Pixels * Total_Vertical_Pixels * Refresh_Rate
- vid_clk used by FPGA core VIP design = the clocking setting vary depend on symbol per clock and pixel clock
- ls_clk used by HDMI IP = the clocking setting vary depend on vid_clk and bit per colour (bpc)
Note : refer to below HDMI user guide doc page 76 (table 36 - HDMI source interface) for the detail explanation.
Another quick guideline with summary table can be found in same user guide doc, page 37 (table 15 : HDMI PLL Desired Output Frequencies for 8-bpc Video)
- You can just refer to the 2 symbol per clock section for Cyclone 10 GX device
- TMDS bit rate or transceiver data rate per channel can be derived from HDMI per channel bandwidth calculation
- BW = pixel clock * (bit per colour + 2)
Thank you for the response!
I did not notice page 37 about the output frequency.
From Table 15, seems like the transceiver refclk needs proper values for different resolutions.
The input reference clock needs change dynamically.
If I am going to have a fixed reference frequency input at 148MHz like hdmi_vip project, how could I find correct setting values for fPLL and IOPLL?
I have shared with you the PLL output ls_clk and vid_clk formula in previous update.
the detail explanation is captured in HDMI user guide doc page 76 (table 36 - HDMI source interface)