I'm working on a DECA development board and I'm trying to transfer data from a FIFO to the on-board DDR3 through a Scatter Gather DMA and an EMIF controller for the DDR. The data are correctly transferred, but not at the maximum throughput. The avalon interface used to send data to the EMIF works at half rate (150 MHz in my case). The DMA works at 150MHz too. I checked the velocity transfer through SignalTap and I noticed that for each data accepted by the EMIF, it asserts the “waitrequest” to the DMA for 4 clock cycles even if the “ready” signal is high, reducing the transfer rate to the DDR.
Hi the ready signal that you mentioned here is avl_ready from the DDR3 controller? If this case, seem like the transfer issue is not come from the controller.
I don't think the waitrequest signal is come from the DDR3 controller, the status signal come from DDR3 is avl_ready but not waitrequest. Please check the waitrequest is come from which component and the issue suppose come from it. Maybe the DMA or Qsys interconnect?
thank you for the answer. Yes, the ready signal is the "avl_ready" of the DDR3 controller. The waitrequest is an input for the DMA that is only connected with the DDR3 controller. I supposed that the waitrequest was exactly the avl_ready (actually the NOT of avl_ready), but it seems that they are different. Is it possible that the Platform Designer inserts an adapter that handles this signal?
I will suggest you come out with details description, eg, screenshot of the signaltap and re-post as a new thread in embedded field. Apparently, this is not the DDR3 IP issue because you mentioned the avl_ready signal works.