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Hello friends! I'm trying to transmit data through jesd204b IP and create an example for it. My question: why is it not started? all n_resets are at null. How can I start it?

SArte1
Beginner
342 Views

Arria10gx development kit; quartus prime pro 18.1;

Examole content: 

Both base and phy;

 Duplex;

 subclass 2;

6144 Mbps;

Hard PCS;

Non-bonded;

 153.6MHz

L = 2, M = 2, F = 2, N = 16, N' = 16, S = 1, K = 32

0 Kudos
3 Replies
Nathan_R_Intel
Employee
122 Views
Hie, My apologies for the delayed first response for this forum case; I had a few JESD questions,and missed updating this one. To ensure your design is configured and connected correctly, please use the Quartus generated Design Example. You may refer to the user guide below for Quick Start on generating an Example Design. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-jesd204b.pdf After that please, make sure install the Arria 10 Development Kit Installer Package. Please select the correct reference clock and system clock frequencies using the clock control GUI. This step is also covered in the user guide. You can perform the Test to check the operation of JESD IP using the tcl included in the Example Design. The steps are also covered in the user guide. Please check if this enables your design to work. Regards, Nathan
bitwise
New Contributor I
122 Views

​Assuming you followed the reset guidelines in the transceiver user guide, then likely causes of not starting include

(a)  PLL's not locking due to reference clock frequency, termination, i/o standard, or signal integrity.

(b)  Improper I/o standards (JESD typically uses CML) and/or terminations on the JESD lanes.

(c)  Core is stuck in synchronization mode, which will be indicated by the dev_sync_n line stuck low.

(d)  The JESD sysref is not being driven properly during the synchronization stage.

 

In my opinion the most useful reference design is the one generated by the JESD204B IP; open your instance then use the "Example Design" tab to set options and generate your own example design.

Nathan_R_Intel
Employee
122 Views

Hie,

 

I agree that the most common problem is related to core stuck in synchronization mode (sync_n not asserted) and tx_sysref pulse not present.

 

Did you manage to get the JESD link up?

 

Regards,

Nathan

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