In order for me to assist you.
Could you provide more info:
When you couldnt instantiate PLL, i believe all logics that was driven by your PLL was synthesized away. That's why it can fit.
I believe now that you can successfully instantiate your PLL, your logics are NOT synthesized away anymore. That's why you CANNOT fit.
In that case, you will have to revise your design to lesser resources or select a larger device.