Arria10gx development kit; quartus prime pro 18.1;
Both base and phy;
L = 2, M = 2, F = 2, N = 16, N' = 16, S = 1, K = 32
Assuming you followed the reset guidelines in the transceiver user guide, then likely causes of not starting include
(a) PLL's not locking due to reference clock frequency, termination, i/o standard, or signal integrity.
(b) Improper I/o standards (JESD typically uses CML) and/or terminations on the JESD lanes.
(c) Core is stuck in synchronization mode, which will be indicated by the dev_sync_n line stuck low.
(d) The JESD sysref is not being driven properly during the synchronization stage.
In my opinion the most useful reference design is the one generated by the JESD204B IP; open your instance then use the "Example Design" tab to set options and generate your own example design.
I agree that the most common problem is related to core stuck in synchronization mode (sync_n not asserted) and tx_sysref pulse not present.
Did you manage to get the JESD link up?