Help!! Error message

[Altera_Forum]

Hi, when i compile my simple design i get the error as such: 

 Error reported by S-function 'sGeneric' in 'wateva2/Parallel Adder Subtractor': Loop detected while propagating bit widths for wateva2/Parallel Adder Subtractor:r.Type was previously FRAC [7, 2], but is now being changed to FRAC [9, 10].    http://img396.imageshack.us/img396/8224/errorjr5.jpg

[Altera_Forum]

HI Clare 

 Sorry I can't fully make out your schematic but it looks as though you have a combinatorial loop - i.e. signals will just keep whizzing around the loop and make it oscillate. If you have feedback in a lump of logic then it must be registered somewhere to prevent this instability occurring.  On the other hand if you do have a register in there and I'm being blind then I do apologise.  Are you using a schematic or HDL?  Cheers  batfink

[Altera_Forum]

actually is a filter design using following equation: 

 w(n) = ay(n-1) + by(n-2) y(n) = w(n-1) + x(n)  = ay(n-2) + by(n-3) + x(n)     is a dsp builder using simulink. is not hdl. i dun have register, only delay function...   so what should i do?

[Altera_Forum]

You're right - it's not a combinatorial loop since there is a delay in the loop. 

 The error occurs during type propagation. The problem is that every block in the loop is set to infer its type, which means that DSPB will attempt to set each block to the minimum bit width required to not lose any precision. However since you have a loop in there, the precision required is actually infinite. DSPB doesn't detect this directly, instead its propagation widens inputs iteratively until they stabilise. With a loop like this, it would iterate infinitely. DSPB tries to detect this infinite propagation and when it does, it gives this somewhat cryptic error message.   Anyway to resolve the problem for this design, you should manually set the bit width on either of the 2 adders or the delay in between them. (You could do it on the gain blocks or their preceding delays, but then you would have to do it twice).

[Altera_Forum]

hmm...actually i dont quite get it..im very new in dspb..can you explain how to manually set the bit width? thanks alot! sorry for the trouble

[Altera_Forum]

To set the bit widths, double-click on one of the blocks I mentioned. Then select the type parameter: this will currently be set to inferred and change it to something else like Signed Fractional. Then set the bit width left and right fields to some values. 

 If you still can't solve the problem, feel free to upload your design and we can take a look at it. Unfortunately a picture of the design leaves out a lot of information.

[Altera_Forum]

thanks..i upload my file. can help me take a look at it?

[Altera_Forum]

Ok I've checked your design and it's a bit more complicated than I first thought. 

 With the current blocks in your design, it is not possible to set the bit width explicitly. The Gain block has bit width parameters, but these control the width of the multiplicand and not the output which is still inferred.  To break this loop, you will need to insert a new block: Go to the library browser. Select Altera DSP Builder Blockset -> IO & Bus -> AltBus. Drag this block to your design and put it between "Parallel Adder Subtractor1" and "Delay". Double click on the new block and set its type and bit width.  Now when you run you will get a new error, this is because you have connected the DSPB "Single Pulse" block to the input port of a "Input" block. This is not directly allowed (there are ways around it but probably best ignored for now) and instead you should use a source from the main simulink library.  I would strongly recommend reading the DSPB documentation and working through the tutorials.  Hope that helps!

[Altera_Forum]

things are getting so complicated. can where can i grab a good DSPB documentation and tutorial practice for me to start learning?

[Altera_Forum]

It's actually not that complicated. The error was caused by the fact that first adder couldn't determine how many bits it needs for the second input port (it was growing each iteration of the loop, due to the feedback adder). As dabuk correctly pointed out, you need to use an altbus block to set a fixed resolution for that input port, that way, the tool would know how to interpret it properly. 

 If you want to read up more about it, I would suggest starting with the DSP Builder User Guide, especially the design rule section (section 3 I believe). Also, DSP Builder comes with a lot of pre-built designs and demos, which will help you get up to speed. The pre-built designs are located under the default installation directory (C:/altera/80/quartus/dsp_builder/DesignExamples). Also if you want, you can simply type "demo" at the matlab command prompt to bring up the list of demos that came prepackaged with DSP Builder.   Hope that clears it up a bit...   I would recommend the DSP Builder User Guide... Specifically the section on the Design Rule... There is one particular rule that describes what you are seeing...

[Altera_Forum]

ok ok...i will go through those material before i proceed. i guess i really lost right now! thanks alot for the advice and guide!!