Seems like ast_sink_ready de-asserts by itself (for a brief moment of time initially) for pretty much all of the DSP IPs (FIR, FFT, VIPs... etc.) I dugged around and I think I found the reason for it.
There is a fifo at the avalon sink (input side) for flow control. This is a small fifo of a certain depth (I believe the depth varies for different cores, usually it's five for FIR). After reset, the avalon controller checks the status of the FIFO. If it sees that the FIFO is empty, it asserts the ast_sink_ready. This is why ast_sink_ready asserts initally.
However, pretty much all the cores only get enabled after there is at least one valid data in the FIFO. Due to the latency involved in the control logic, the FIFO gets filled quickly until the design start fetching input data from the FIFO. Therfore, for some cycles ast_sink_ready signal is de-asserted to allow design to use the data in the FIFO.
