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Help! Implenting a Cmex S-functions into your FPGA

Altera_Forum
Honored Contributor II
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Hello all 

 

I was wondering if any one has managed to get Signal compiler in simulink to actually compile and convert your S-function to VHDl. 

 

I have completely hit a dead end and cant find any good documentation on successfully adding a custom built S-function into your FPGA. I was hoping some one could help me. 

 

I have tried numerous things:- 

 

1. Simply added the s-function into my simulink design, the signal compile complained that its out puts could not directly drive alt blocks. 

 

I am not sure what this error means but i simply added not gates infront of them but the error persisted. 

 

2. I tried putting my s-function into a subsystem and then run signal compiler. 

This time when coverting to VHDL stage I get the following error:- 

 

Unable to create subsystem HDLSubSystem.vhd Error: Entity HDLSubSystem -> block Output: Input pin(1) is not connected to an Altera Block. Error: Entity HDLSubSystem -> block Output1: Input pin(1) is not connected to an Altera Block. Error: Entity HDLSubSystem -> block Output2: Input pin(1) is not connected to an Altera Block. Error: Entity HDLSubSystem -> block Output3: Input pin(1) is not connected to an Altera Block.  

 

I hope some on can help me, it will be greatly appreciated. I will attach with this pose a copy of the sfunction, which simply suppose to read two input data values and spit the corresponding rgb values. 

 

thanks
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Altera_Forum
Honored Contributor II
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Firstly you don't mention it, but I assume you're talking about DSP Builder. Secondly it isn't possible to convert your s-function to VHDL since that would require a C to HDL tool with specific knowledge of simulink/matlab. 

 

On the other hand you can create a "blackbox" subsystem containing your s-function and tell DSP Builder to use your own HDL file when it tries to generate the system. To do this you create a subsystem with HDL Input blocks directly connected to the inputs of the subsystem and HDL Output blocks connected to the outputs. You then create an HDL Entity block which will point to HDL File. You need to name HDL Input and Output blocks according to the port names in your HDL entity. 

 

Then when you simulate, it will use your s-function but compilation will use your VHDL file.
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Altera_Forum
Honored Contributor II
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Thanks Dabuk, 

 

Your hints realy helped me find some info online, but I am still running into some problems. 

 

I have done as you said, created a black box using Subsystembuilder block in simulink using a vhdl file containing an entity block.  

 

If you have the time i was hoping you could check if Ihave done the right thing. Basicaly Now signal compiler does convert to VHDL but fails on synthesis and fitting.  

 

I am not to sure what the VHDL Entity file should contain. Does it only need and entity declaration or also an architecture?  

 

If it does need an architecture how am i suppose to wire up the signals... I hope you reply i need desperate help and realy appreciate your response. 

 

Regards, 

Nadeem
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Altera_Forum
Honored Contributor II
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I'm really no expert on VHDL, so hopefully someone else can chime if I get anything wrong here. 

 

The file you specify here should contain all the HDL necessary to synthesize the block. So I assume it will need the architecture. (It is possible to have your black box use more than one VHDL file, but it requires creating tcl scripts to compile those files in Quartus and ModelSim). 

 

Not sure what you mean by last comment. DSP Builder will wire up the signals since it knows the names of the ports/clock/reset of your entity. If you mean internally in your entity, well then that kinds of up to you... :) 

 

Hope that helps
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Altera_Forum
Honored Contributor II
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Hello Dabuk, 

 

Still Cant solve this problem. 

 

I was wondering if you have any links or tutorials on this or an example ? 

 

thanking you nadeem
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Altera_Forum
Honored Contributor II
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The best I can do is to point you to the user guide: 

 

http://www.altera.com/literature/ug/ug_dsp_builder.pdf 

 

Look for chapter 9 and explicit black box interfaces. Other than that I would suggesting posting your design - it's hard to say what's wrong without a simulink model.
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Altera_Forum
Honored Contributor II
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Oh thanks Dabuk, I have read the section 15 times LOL. 

 

But I will send you my MDL files hopefully you can tell me where i am going wrong. 

 

It simulates fine and as as converts it to VHDL but it fails on Synth and fitting. 

The following error is shown in the DSP Report file : 

Convert Mdl to VHDL : PASSED  

Synthesis : FAILED Timestwo.map.rpt  

Quartus II Fitter : ---------  

 

Quartus II Map Log 

 

Info (10544): VHDL Assertion Statement information at Timestwo.vhd(71): assertion "" DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 6.0"" is always false 

Info: Elaborating entity "SBF" for hierarchy "SBF:Outputi" 

Info: Elaborating entity "sAltrPropagate" for hierarchy "SBF:Outputi|sAltrPropagate:u0" 

Error: Node instance "timetwoi" instantiates undefined entity "timetwo" File: C:/Nadeem_work/Matlab Tutorial/TimesTwo/Timestwo.vhd Line: 105 

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning 

Info: Allocated 135 megabytes of memory during processing 

Error: Processing ended: Wed Feb 20 11:42:24 2008 

Error: Elapsed time: 00:00:01 

 

I have Attatched the following:- 

 

Timestwo.mdl --- the simulink model file 

Timestwo.VHD -- the top level entity file used to creat subsystem builder black box 

timestwoc.txt-- is the s-function. this file has to be renamed to timestwo.c. 

 

I realy appreciate you time and look forward to hear from you soon . 

 

regards
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Altera_Forum
Honored Contributor II
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This is a DSP Builder 7.0 design. I would strongly recommend you upgrade to DSP Builder 7.2. DSP Builder was completely rewritten in 7.1 and 7.2 and its service packs have further improvements. My previous comments in this thread assumed you had 7.1 or 7.2 so it's not surprising they weren't so useful. 

 

As to your compile error it's because this line appears in the generated source: 

 

assert (1<0) report altversion severity Note; 

 

Since 1 is rarely less than 0, this file will not compile. I don't have DSP Builder 7.0 so I can't tell you why this happens.
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Altera_Forum
Honored Contributor II
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Thanks Dabuk, I decided to just right it in VHDL:) thanks for your time though

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