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Altera_Forum
Honored Contributor I
850 Views

Help request for FLASH remote programming

Hi, 

 

 

I'm planning a card, with a Cyclone III device, and that device will have to communicate with an external card through a local bus. The application will reside inside an Intel FLASH, as recommended in the Cyclone III book.  

I would like to be able to make a remote programming to the FLASH. i.e, to send a file from a remote location to the controlling card, from there to the FPGA inside my card, and on to the the FLASH.  

As I read it in the Cyclone III book, When I burn the FLASH through the JTAG, at my site, then I instantiate a loader from Altera, called PFL. I'm looking for such a loader (in Verilog or VHDL), that is already working in a design, to operate the state machine, working with the FLASH.  

I can write the simple state machine, but as I understood it, the FSM operates with conjunction with the dedicated circuitry in the FPGA, so I would like to see a reference design that is already working. 

Does anyone has such a loader in Verilog, or even in VHDL? 

I'll be mostly gratefull if you could share it with me. 

 

 

 

 

Best Regards, 

Eldad
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6 Replies
Altera_Forum
Honored Contributor I
48 Views

Hi efargon, you can refer to AN521 

 

http://www.altera.com/literature/an/an521.pdf 

 

for your application. The Parallel Flash Loader (PFL) is an Altera Megafunction directly available in Quartus II (altparallel_flash_loader). 

 

Cheers 

OD
Altera_Forum
Honored Contributor I
48 Views

Hi, 

 

 

Thanks for your letter. AN521 deals with putting 3 files into one POF file and burning them through a local JTAG. I need to write a user-logic that will reside inside my FPGA, and upon triggeriing from an outsdie controller card will receive the bytes of the a new configuration file, and I would like to write those bytes to a parallel CFI flash(remote update function). The external controller card receives the new configuration file via a TCP/ IP protocol from an extrnal site. My FPGA is a Cyclone III device and I work in an active parallel mode to program the CFI Flash device. Can I still use the altparallel_flash_loader megafunction? How? Can I just take the bytes I receive, one by one from the external controller card, and 'give' it to the altparallel_flash_loader megafunction that will write them to the parallel CFI flash? What will trigger the altparallel_flash_loader megafiunction to make this writing to the Flash? 

I'd appreciate if you could guide me here, or even point me to a reference design that does a similar job. 

 

 

Sincerely, 

Eldad Fargon 

efargon@yahoo.com
Altera_Forum
Honored Contributor I
48 Views

What you are trying to do is actually quite straightforward but it sounds like you're probably a little new to FPGA design and therefore a bit overwhelmed by the components. Here are the components you need to figure out. 

 

1 - Communication between your controller card and the FPGA. This is entirely up to you. You kind of need to figure this out first. Are you going to use some existing protocol to deliver information back and forth between the controller card and the FPGA? A typical approach is to simply provide a standard processor interface from the controller card and the FPGA (address, data, write, read, etc.). Then in the FPGA you memory-map the various components that you want the controller card to access. Then the controller card sort of has direct access to the Flash memory and whatever else you want it to acess. 

 

2 - A CFI flash controller. You can either write your own or get one from a third party. A second option would be to use SoPC builder, a NIOS II processor, and the Altera-provided CFI flash component.  

 

3 - Depending on how you're going to implement 1 & 2, you need to figure out how to connect the two together. How are you going to bridge between the Flash controller block and the "controller-card communication" block? 

 

So, those are the basics of what you're going to have to figure out. As far as actual implementations, I and many others on the forum can provide you with ideas of what we have done in the past. However, you are going to need to know what the communication path between the controller card and FPGA is. 

 

Jake
Altera_Forum
Honored Contributor I
48 Views

Hi Jake, 

 

 

Thanks for the letter.  

I already defined, and in the middle of writing in Verilog stage No. 1: the interface (communications) between the external controller and my FPGA. It's a set of registers (data to write, chunk length, because the bytes are written in chunks, session trigger register etc.). Basically, every time I'm about to write a byte, the controller writes me the next byte, inside my FPGA, and I'm in the middle of writing the interface to the external controller, thta will alaso communicate with the controller to the CFI Flash. 

 

What I miss is some guidance for stage 2: the controller that handles the writings to the CFI Flash. I have some questions regarding this controller:  

1. There are some commands in the Intel Flash (suspende, erase, program...). Which commands do I have to implement?  

2. I saw the 'program' command, but it says in the datasheet that it's comprised of two cycles. The first cycle is the address writing but the data bus, during the address writing, is supposed to hold one of two values: 10/ 40. Which value do I have to put on the data bus: 10 or 40 (I'm relating to the Intel StartaFlash)? 

3. Is this a simple state-machine, because I recall that in the Flash writing there is some algorithm running to make sure the right data was written to the right address. Do I have to implement that algorithm?  

4. Are there any indications/ alarms you can recommend me to put in my deisgn to make this state machine more efficient? 

Is there a reference design to this, since I don't have a NIOS system.  

 

 

Thanks for the attention. 

 

 

Best Regards, 

Eldad Fargon
Altera_Forum
Honored Contributor I
48 Views

Okay I understand where you are at now. I have written the controller that you are trying to write.  

 

1 - Basically you need "erase" and "program". You will also need to poll status. You can either do this by reading the status register (recommended) or at minimum you can use the status pin from the flash. At minimum, you need to be able to determine when an erase/program cycle has completed. Beyond that, you may want to read the status register to know if the command succeeded. Are you also going to implement read?  

 

2 - If memory serves, you can use either 0x10 or 0x40. I think either work fine at this point. At some point in history, it seems like you had to use one or the other depending on whether you were in x16 or x8 mode but I don't think that's the case anymore. 

 

3 - The state machine isn't really complicated but there are kind of a lot of states. I don't think I have a copy of the one I wrote anymore because years ago I replaced it with a NIOS. When I get home tonight, I'll see if I can find the one I wrote years ago but I doubt it. You may actually want to consider doing this in a NIOS. It may actually take a comparable amount of logic resources and the code is very simple. I've attached the c code that I currently use to interface to an Intel J3 v. D NOR flash. 

 

4 - As you start writing the machine, you'll notice there is a lot of redundancy in the states So you'll likely want to break the state machine up into two or three layered state machines. 

 

Jake
Altera_Forum
Honored Contributor I
48 Views

Hi efargon, 

 

I am also looking to implement the flash controller in MAX2 cpld.even though presently we are using PFL from altera we need to program the flash from the processor,which will send the configuration file via SPI interface to CPLD.if you have already implemented this code can you send it to me? 

 

Thank you, 

Regards, 

Ramesh.B
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