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How To do 90' shift alignment with Data and wrt out_Clock in ALT_LVDS TX ip.

Altera_Forum
Honored Contributor II
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Hi all,  

 

I'm Lalith , Im using ALT lvds TX Ip (7 bit serialisation , 329 Mbps line rate ) in my design with cyclone 4 device. integration of IP is done but as per my other side device . I need total 90 degree shift with output data and out clock . but Ip o/p is at 45 degree shift only .  

 

how to shift my Tx_Out data by 45' extra (total I need 90') with respective Tx_out_clk (from +'ve edge) . ??  

 

attachments : simulation window Screen shot.  

 

Thanks in advance 

Lalith
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