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MSGDMA transfer irregularities - Cyclone 5

Altera_Forum
Honored Contributor II
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Hi, 

 

I have a hybrid system where an MSGDMA MM-ST reads data from DDR3 SDRAM to a custom made component on the FPGA that filters the data.  

Simultaneously another MSGDMA ST-MM reads the output back to the DDR3 SDRAM. 

They each use a port of the fpga2SDRam bridge. The whole system (including bridges) works at 100 MHz.  

 

My problem is with the DMA writing back the data to SDRAM. If the quantity to transfer is large, it sometimes truncates or even reorders data as  

it is writing it back !  

 

Is this normal ? Are there any solutions to this ?  

 

Thank you in advance
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