How can I change Input Pins Default Value?

[AChog]

I used verilog HDL code to write my program in Quartus II for FPGA Cyclone II. I realized input pins are set High by default when they are unconnected. This makes a big problem when for example a wire is disconnected in our system. How can I set the default value to 0 or GND?

[YuanLi_S_Intel]

Hi Amin, You may change the state of the unused pin in FPGA. To do so, go to Quartus -> Device -> Unused Pin -> input as tri-state. If the pin is used but it need to be disconnected, i think the best way to change the state of the pin is to write a logic for this. Regards, YL