We are clocking the Generic Serial Flash Interface IP at 156.25 MHz on a Cyclone-10GX, with a clock divider of 4. We can configure the chip select delay before the first clock, and after the last clock, but the chip select high time between commands is too short for our flash.
Our SPI Flash requires a minimum of 6 ns between read operations, and a minimum of 30 ns between program or erase operations.
Using SignalTap, this appears to be two cycles with the IP so 12.5 ns. Read operations are successful, but the when writing, the status poll is perceived as part of the program operation, because the SPI flash misses the chip select going high.
Is there a way to configure how long the chip select stays high after a program or erase command?
You will be able to set the Chip Select delay on the IP by changing the setting on offset 2. Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf Table 3.
I'm sorry but as far as I can see the chip select delay is only configurable between the chip select assertion and the first clock and between the last clock and chip select de-assert. Both from signal tap and by inspecting the generated code, it looks like the time between operations is always two clock cycles. We have been unsuccessful in changing this with these register settings.
We are using this IP with several flashes
The only solution that seems to work for us is reducing the input clock to the IP to make sure the two clock cycle inactive time is long enough. This again means that the maximum QSPI clock frequency we can use is 19.5 MHz, which quite unfortunate when reading works at 78 MHz.
For Micron MT25Q, you can stll used the Serial Flash Controller Interface IP which we have verified. In order to enable it you may refer to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/compon.... For Winbond flash, the only solution is to use Generic Serial Flash Interface.
May I know if you are facing issue during read? If yes, you can still modify the read delay.
I'am facing the same problem.
I use the Generic Serial Flash Interface IP to access an EPCQ256 flash. The internal clock provided to the IP is 100MHz.
The IP does not respect the timing characteristic of the EPCQ256 for the chip select high time (Tcsh = 50ns min in the datasheet). I checked with a scope, and the chip select high time is 20ns.
Fortunately, it works for the read and write operations, but it failed for the sector erase or chip erase operation.
The best way to solve this issue would be to add a parameter in order to configure this chip select high time.
I tried with your settings, and it does not work. (error in read values, write operations not working)
With your settings, the chip select high time is 30ns and does not respect the EPCQ256 datasheet (50 ns min).
I think it is only a question of chip select high time. I increased the time between two commands sent to the IP in order to increase the CS high time, and it works for all commands (sector erase, chip erase...).
Are you saying, that everything work fine with the below setting? If yes, then can you use the setting to move forward?