I have set up a design with two TSE IP units. My goal is to send ethernet packets from one TSE MAC to a second TSE MAC.
I have already the design working in simulation, but somehow it doesn't work on the FPGA.
I have both TSE MAC's configured in 100Mbit and RGMII mode. I have enabled only one MDIO interface which I use to set the 88E1111 PHY registers.
For sending UDP packets I use the ethernet packet generator PackETH.
For monitoring the two Ethernet ports on the FPGA I use Wireshark.
So when I send packets to an Ethernet port I only see the packets sent on the Ethernet port, but they are never received on the second Ethernet port.
Do you guys now what possibly could go wrong?
How can I find the problem, since it does work in simulation?