We are using manual instantiation of the DCFIFO in the SystemVerilog for the clock crossing between two asynchronous clocks (no relation between the clock).
Since the write and read clocks are not synchronous or in any other relation, we have them in two different clock groups in sdc and we do not define any other constraints for the FIFOs.
In the previous projects, this approach worked reliably and we did not experience any problems with designs. However, our current project exhibits strange behaviour.
According to the https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd02232015_507.html the embedded constraints do not work correctly. Was the issue solved?
Moreover, I discovered, that when Platform Designer instantiates DCFIFO inside interconnect, it includes SDC file with following comment:
# Do not declare the FIFO clocks as asynchronous at the top level, or false path these crossings,
# because that will override these constraints.
Does this mean, that we should not have the read clock and write clock in different clock groups?
My current understanding of the issue is that to correct implementation of DCFIFOs, we need to remove all clock groups and place the constraints from page 23-24 of ug_fifo.pdf for all dcfifos in the design. Is this correct? It seems, that Platform Designed uses slightly different constraints in generated SDC file.
We have relatively large design and we are near to the project deadline, therefore before we start to rewrite our constraints, I would like to know what is the right approach.
I would also appreciate the answer from someone from Intel so that we may be sure.
Thanks for your comments