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FZOVK
New Contributor I
835 Views

Problem with PCIe writes on Arria 10 development board

We have the DK-DEV-10AX115S-A Arria 10 development kit and are connecting it to a Linux PC via PCI Express. We have reconfigured the Arria 10 with our own code, which contains the "Avalon ST interface for PCI Express" IP, and we are using a 256-bit interface with 32-bit address. We have created RAM and registers inside the FPGA that can be accessed over the PCIe interface from the Linux PC.

 

We have found that we can write 32-bit values to the FPGA reliably, but there is a problem with writes of 8 and 16 bits: they will corrupt the other bytes in the 32-bit range they occupy. For example, if we write a 32-bit value to address 0xF000 within the PCIe space, we can read that value back reliably. However, if we write an 8-bit value to 0xF000, 0xF001, 0xF002, or 0xF003, we will find that the other three bytes in that range will get corrupted. 16-bit writes are broken in a similar way.

 

All indications are that reads always work reliably as well. Does anyone have any thoughts on what could be causing this problem, or what else we can look at? Thank you for your help.

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3 Replies
SengKok_L_Intel
Moderator
47 Views

Hi Frank, I believe the minimum payload for PCIe in Avalon ST interface is 1 dword, and which is 32 bits. Regards -SK
FZOVK
New Contributor I
47 Views

Thank you, SK. Is there another way to use the PCIe so that we can write individual bytes?

SengKok_L_Intel
Moderator
47 Views

Hi,

 

​1 idea is that,  you may perform read modify write. Read the 32 bits from the register, and mux with the data that you wish to keep , and then write it back to the register.

 

Regards -SK

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