FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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How can I troubleshoot two Triple Speed Ethernet IP's on an Altera MAX10 FPGA?


Hi guys,


I have set up a design with two TSE IP units. My goal is to send ethernet packets from one TSE MAC to a second TSE MAC.

I have already the design working in simulation, but somehow it doesn't work on the FPGA.

I have both TSE MAC's configured in 100Mbit and RGMII mode. I have enabled only one MDIO interface which I use to set the 88E1111 PHY registers.

For sending UDP packets I use the ethernet packet generator PackETH.

For monitoring the two Ethernet ports on the FPGA I use Wireshark.


So when I send packets to an Ethernet port I only see the packets sent on the Ethernet port, but they are never received on the second Ethernet port.


Do you guys now what possibly could go wrong?

How can I find the problem, since it does work in simulation?




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2 Replies
Hi Mansur, You may want to try with lower level debug on TSE MAC first. Example like performing loopback testing to see where is the failure point. 1) Loopback within TSE IP 2) Loopback on External PHY chip 3) Then only finally loopback on external host second FPGA side. If loopback is working then most likely is your higher level software application layer issue. Sim working is a good sign. That tell you most likely the setting is correct. Then you can compare what's difference on sim vs actual hardware like how do you sim external PHY and second FPGA ? Could the problem resides there ? Thanks. Regards, dlim
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Thank you dlim !

I will try this out.





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