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How can be Generate Accurate 622.08MHz(For STM-4 application) clock in ArriaV PLL with the help of input clock 77.76 Mhz

Vsing44
Beginner
256 Views

This is regarding the clock (622.08 M) generation issue from ArriaV PLL.

Input clock is 77.76 Mhz to PLL block. Expected PLL output clock is = 622.08 Mhz, But Actual generated clock is 622.28 Mhz. Pll clock is constraint by using “derive_pll_clocks”. Please see the attached screen sort for PLL configuration

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1 Reply
Rahul_S_Intel1
Employee
100 Views

Hi ,

I am working internally on the above request

 

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