This is regarding the clock (622.08 M) generation issue from ArriaV PLL.
Input clock is 77.76 Mhz to PLL block. Expected PLL output clock is = 622.08 Mhz, But Actual generated clock is 622.28 Mhz. Pll clock is constraint by using “derive_pll_clocks”. Please see the attached screen sort for PLL configuration