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HBhat2
New Contributor I
212 Views

Initial Data is missing in the receiver side of Stratix 10 Native PHY

Hi,

We have developed a custom PCS for TBT3 (Thunderbolt-3) like protocol. I am able to test and receive a protocol specific packet continuously in stratix 10 SoC Dev kit. Going forwards, I need to send different protocol symbols in a sequence and I am testing this in Simulation before testing it in the hardware

While carrying out the simulation[Custom PCS-TX->PMA-TX,ATX-PLL, Reset Controller -> (Loopback at serial line) -> RX PMA -> custom word align logic -> Custom PCS-RX], I am seeing that initial 256 parallel data is missing in the received rx_parallel_data bus which is output from PMA-RX.

In the TX side, I am sending the data whenever tx_ready = 1 and receiving the data whenever rx_ready and rx_valid are high.

PMA is in Basic( Enhanced PCS) mode with 64 bit PCS data width with custom word align logic (not using in built bit slip logic)

 

Any idea what is the reason for initial data miss (256, 64-bit data)?

 

With Regards,

HPB

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5 Replies
HBhat2
New Contributor I
61 Views

Hi,

 

I noticed that there is a "tLTD" timing, which is 4us minimum as per startix 10 device data sheet. Whether this "tLTD" causing the data miss in the receiver side?

If "tLTD" is the cause, then I should consider "tLTD" = 4us or 5us (minimum) ? Reason being, in L-tile user guide "tLTD" is being mentioed as "minimum duration of tLTD of 5us".

 

With regards,

HPB

CheePin_C_Intel
Employee
61 Views

Hi HPB,

 

As I understand it, you observe some data missing from the RX parallel data output in the simulation. To facilitate further debugging, would you mind to:

 

1. Create a simple test design without using your custom PCS. Try to send fix parallel data to the TX PMA and loopback to RX PMA to see if you are able to get back the same parallel data (with incorrect word boundary). You may not need to send 256. Probably 3 will do after the rx_ready go high. You may test this in Modelsim simulation.

 

2. If the design in #1 is able to replicate missing parallel data, please help to share with me the simulation files together with steps to replicate the simulation. I would like to take a look to get a better understanding.

 

3. Please share with me the Native PHY .ip file so that I can have understanding on your configuration.

 

4. What is the specific S10 device and Quartus version that you are using currently?

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

CheePin_C_Intel
Employee
61 Views

Hi HPB,

 

Regarding your inquiry on the tLTD, for your information, the rx_ready will be asserted after the tLTD and digitalreset go low. Therefore, if you are sending data after rx_ready go high, I think it is not the cause to the data missed that you are observing. We can isolate this for the moment and revisit if required after we test with the simulation without custom PCS.

 

Thank you,

HBhat2
New Contributor I
61 Views

Hi @cheepinc_Intel​ ,

 

Yes, I have done the PMA only simulation and done 2 types of simulation.

1) Sending data before rx_ready asserts

2)Sending data after rx_ready asserts

 

and I observed that there is no data loss when I send the data after rx_ready gets asserted (type 2 simulation).

 

All the previous simulations I carried out with my custom PCS is Type-1 simulation where our intention was there is no relation between TX and RX.

And this is not a problem in our real hardware as the protocol does not send any data to Transmitter as soon as power up.

 

Thank you for your clarifications.

 

With Regards,

HPB

CheePin_C_Intel
Employee
61 Views

Hi HPB,

 

Thanks for your update. Please correct me if I am wrong, as I understand it, your simulation is working fine now if you are sending data after rx_ready is asserted.

 

Please let me know if there is any further inquiry that I can help. thank you.

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