Migration of Altera SDP memory to Xilinx SDP Memory.
Please find attachment . Here my question is when we are migrating from altera sdp memory to xilinx memory existing design having screenshot 2 settings in the attached file. What are the default options for output1. for when we select single clock and dual clock separate input and ouput clocks output1 option is available .when we are using dual clock use separated read and write clocks output1 option is not available . What are the default options available we we are not getting output1 tab (old contents appear or dont care ) . Please support on this . Please refer the attachment . Please suggest me what is the difference of dual clock : separate input clock and ouput clock and dual clock : separate read and write clocks . when we are migrating from Altera to Xilinx will both same or different ?