FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

How change the memory size in PCIe Hard IP in Qsys

Altera_Forum
Honored Contributor II
788 Views

I have successfully generated the Altera cyclon4GX PCIe gen1 x4 HardIP example using PCIe compiler in Qsys with on chip memory and DMA using Quartus 11.  

Pci express core contains the following BARs 

 

(1) BAR0 - Contains 27 bit (auto) prefetchable memory that can support upto 128MByte of memory 

 

(2) BAR2 - Contains 27 bit (auto) non-prefetchable memory that can support upto 128KByte of memory. 

 

I would like to change the BAR0 and BAR2 to support much lower size may be 128MBytes of memory. I am not sure how to change this value ?
0 Kudos
0 Replies
Reply