Hello Guys,I have designed a simple VIP designed with QSYS. The design has The following IPs: Frame_Reader, Sequencer, LPDDR2 and ITC. My question is, how do I properly constrain the design? It Looks like each one of the IPs generated has its own .sdc Which I assume is loaded in automatically by Quartus. The timing analysis fails and I am getting inconsistent behavior With every build especially the LPDDR2. Thanks for your help, S.