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Altera_Forum
Honored Contributor I
743 Views

How do I constrain VIP (QSYS) build?

Hello Guys, 

 

I have designed a simple VIP designed with QSYS. The design has 

The following IPs: Frame_Reader, Sequencer, LPDDR2 and ITC. 

My question is, how do I properly constrain the design? It 

Looks like each one of the IPs generated has its own .sdc 

Which I assume is loaded in automatically by Quartus. 

The timing analysis fails and I am getting inconsistent behavior 

With every build especially the LPDDR2. 

 

Thanks for your help, 

S. 

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Altera_Forum
Honored Contributor I
45 Views

Another question, how do I Signal-Tap inside the QSYS block? 

 

Thanks, 

S.
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