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Hello,
When simulating a Cyclone 10 GX Verilog design in Modelsim, I'm getting the following error when instantiating the design:
** Error: (vsim-3033) Instantiation of 'altera_a10_xcvr_clock_module' failed. The design unit was not found.
All the other IP blocks are found / instantiated.
I'm wondering if I need to install the Arria libraries.
Also, we're using a non-paid license for the Cyclone 10 GX.
Thank you
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Thank you for the reply.
I wasn't able to find the library for altera_a10_xcvr_clock_module.
However, since it provides no functionality to a simulation, the simplest path forward was to define it out with our SIMULATION directive.
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Hi,
As I understand it, you observe some problems with the C10GX Modelsim simulation. To further narrow down the problem, you can do the folloiwng:
1. Look through the Modelsim simulation messages to see if there is any compilation error during any library related to "altera_a10_xcvr_clock_module".
2. If it is due to library file not found during compilation, you can look into the simulation TCL files to check from which specific directory is Modelsim looking for when trying to compile the "altera_a10_xcvr_clock_module". Then you can check if this file is available in your local Quartus installation.
3. If the physical library file can be found, but compilation still prompting error, it might be related to the directory path too long, especially in Windows system. You can try to move your design folder to a shorter path directory.
4. If the physical library file cannot be found in your Quartus installation, we might need to further debug into this. You may need to create a simple test design which could replicate this obervation and share with me.
5. Would you mind to further elaborate on the non-paid license that you are referring to? Is it an evaluation license?
Please let me know if there is any concern. Thank you.
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Thank you for the reply.
I wasn't able to find the library for altera_a10_xcvr_clock_module.
However, since it provides no functionality to a simulation, the simplest path forward was to define it out with our SIMULATION directive.
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Hi,
Thanks for your update. Glad that you have found the workaround. Thank you.
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Hi,
This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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