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Altera_Forum
Honored Contributor I
718 Views

How to: Simulate the UniPHY memory controller interface with custom logic ?

Hello, 

 

I've a custom logic which interfaces (in VHDL) with the Avalon interface on the UniPHY controller DDR2 SDRAM, I would like to test it, but I didn't results. 

 

First I tried to edit/connect the simulation project (Verilog) whit my block, after some fails I went to the  

IP Functional Simulations on External Memory Interface Handbook : Volume 4: Simulation, Timing Analysis, and Debugging.  

 

Than tried to use the ddr2 block provide on the <project directory>\<variation name>_sim\<variation name>.vhd 

but the problem is that I have some signals dedicate to memory exe: mem_a, mem_ba, mem_ck, mem_cke..... and I don't know hat to do whit it. 

I went to memory vendors web site and found some memory models: they are in Verilog, second some signals like mem_ck are not compatible (one is std_logic_vector(1 downto 0) ? and the other is a normal wire) 

Does any one know how can I test it ? 

 

Thanks in advance 

 

Rafa.
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3 Replies
Altera_Forum
Honored Contributor I
36 Views

the easiest way is to edit the Example Project generated by Quartus. it instantiates a basic memory model 

 

the project is located a path similar to: 

 

ddr3_core\ddr3_core_example_design\simulation 

 

the file that instantiates the memory controller and example driver is what you want to edit. remove the example driver and add your logic: 

 

ddr3_core_example_sim_ddr3_core_example_sim_e0.v
Altera_Forum
Honored Contributor I
36 Views

Hi,  

Thanks for the tip, only to be more clear, I'll have to replace the : altera_merlin_slave_translator declaration with my block ? 

 

Thanks  

 

Rafa 

 

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Altera_Forum
Honored Contributor I
36 Views

yes, you should be able to ignore the d0_avl_translator_avalon_universal_master bus and just drive the if0_avl_translator_avalon_anti_slave bus

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