FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

mSGDMA with different write clock and read clocks

Fft core generation stuck

FIR Coefficient Reload Problmes

Altera FIR Compiler II 15.0 Coefficients Reload Issues

Parallel Flash Loader For MAX II .

Arria 10 Transceiver PHY latency estimation

PCI-E DMA for Arria 10

Third party LDPC ip Core

FFT output spectrum generation

FFT MegaCore 13.0 Generation Stuck

DE1-SOC hps ddr3 memory

Arria 10 Transceiver Native PHY for simply connection.. problems!

EMIF SDRAM Clock Domain Inquiry

Arria 10 - Reference Design - EMIF Timing Violations

altera_dma driver PCIe under linux

Featured Content

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)