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Honored Contributor I

Arria 10 - Reference Design - EMIF Timing Violations



I am experiencing some instability when using Altera's design reference for external memory dma ( When I use the example driver and user application provided along with the reference design, they work about 90% of the time and then fails for no reason. When it crashes I have to reprogram de device and reboot the host system to get working again. This behavior is observed when I use the reference design alone and also when I add my custom logic to the system.  


My guess is that it is somehow related to timing problems on the EMIF. When I synthesize the reference design I get the following timing report:  



Some clock paths do not meet timing requirements. I have also notice that some constraints on the ".sdc" files are been ignored by the tool:  

I suppose that the reference design should come without any timing violations. Am I doing sth wrong? 


Timing requirements for the reference design are not being met. As I am using the reference design as a template for my main project, I suppose these problems are causing strange behaviors in my logic too. When I synthesize the circuit without the EMIF instance the timing analysis passes without violations and the non-emif-related parts of the circuit work fine. 


PS: I am using Quartus 18.0 to synthesize the reference design. 







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Honored Contributor I

what's your memory type in Arria 10? 

you should change some parameter in reference design in EMIF