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Arria 10 - Reference Design - EMIF Timing Violations

Altera_Forum
Honored Contributor II
987 Views

Hi, 

 

I am experiencing some instability when using Altera's design reference for external memory dma (http://www.alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_with_external_ddr4_-_arria_10). When I use the example driver and user application provided along with the reference design, they work about 90% of the time and then fails for no reason. When it crashes I have to reprogram de device and reboot the host system to get working again. This behavior is observed when I use the reference design alone and also when I add my custom logic to the system.  

 

My guess is that it is somehow related to timing problems on the EMIF. When I synthesize the reference design I get the following timing report: 

 

https://mail.google.com/mail/u/0/?ui=2&ik=75a0d2680d&attid=0.1&permmsgid=msg-a%3Ar9063647983701074467&th=1646548067720e20&view=fimg&sz=w1600-h1000&attbid=ANGjdJ9KUN8KNGNhFCjhZ_DgrrRZ_uJm7IFyvAB8pQELbVgJpqizmoaFQzGfs8guP8PFmO5jkcKe_No3PRPNstlPcZPXyj-bhIcXvFHcLjr-HlNuI0Zl8IL88J1L-UM&disp=emb&realattid=ii_jj73nkte0  

 

 

Some clock paths do not meet timing requirements. I have also notice that some constraints on the ".sdc" files are been ignored by the tool: 

 

https://mail.google.com/mail/u/0/?ui=2&ik=75a0d2680d&attid=0.2&permmsgid=msg-a%3Ar9063647983701074467&th=1646548067720e20&view=fimg&sz=w1600-h1000&attbid=ANGjdJ-7ZpB5sAyStCVDjoassgZUoh4Nqvi6W6XbMwf4dHtTO7Dj5KbQxXuF1varjIGNRoPC5x_2YEoehtsNn2t2nrAQR6g92R9lM2xOyPaZf0Y9-Mcm3n_vWTQ5ni8&disp=emb&realattid=ii_jj73nzcv1  

 

https://mail.google.com/mail/u/0/?ui=2&ik=75a0d2680d&attid=0.3&permmsgid=msg-a%3Ar9063647983701074467&th=1646548067720e20&view=fimg&sz=w1600-h1000&attbid=ANGjdJ8K0ChOCZj2BEaB0w5ELxNmSnEweN56lMfw9pu4HpyqTRrhQb_Vv_9HaKmihGRkZhoZ8huYrM7ABwxUzvxsl9eFh3xTRwkO7vE3VL2zOL6i4EG_BlDHjeOGuy8&disp=emb&realattid=ii_jj73oem92  

 

https://mail.google.com/mail/u/0/?ui=2&ik=75a0d2680d&attid=0.4&permmsgid=msg-a%3Ar9063647983701074467&th=1646548067720e20&view=fimg&sz=w1600-h1000&attbid=ANGjdJ98R07c8UQF3IyksT_qW_eOxN7X-jWdHhP8HaQwerMq1-IHGCzz2yG0gtw5lA31MVc1tyy4A7nOQar3yHRmPbDe4g_nsnn9mWgHxFYhEoQ4qGZWtpszIs6elbs&disp=emb&realattid=ii_jj73rftp3  

I suppose that the reference design should come without any timing violations. Am I doing sth wrong? 

 

Timing requirements for the reference design are not being met. As I am using the reference design as a template for my main project, I suppose these problems are causing strange behaviors in my logic too. When I synthesize the circuit without the EMIF instance the timing analysis passes without violations and the non-emif-related parts of the circuit work fine. 

 

PS: I am using Quartus 18.0 to synthesize the reference design. 

 

Thanks 

 

 

 

 

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Altera_Forum
Honored Contributor II
221 Views

what's your memory type in Arria 10? 

you should change some parameter in reference design in EMIF
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