FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

EMIF SDRAM Clock Domain Inquiry

Altera_Forum
Honored Contributor II
828 Views

Hi,  

 

My goal is to interface my FPGA design with an external DDR3 SDRAM memory using the EMIF IP. I am working off of a sample design, which provided all the parameters for the EMIF (memory clock frequency, timing parameters, etc). In particular, the parameters "Memory Clock frequency" is set to 1066.66MHz and the "Clock rate of user logic" is set to quarter rate. I believe this signifies that the EMIF provides an "user clock" of frequency 266MHz, which I am meant to use to clock my design.  

 

My question is as follows: What is the best practice if I want to operate my FPGA design at a different frequency than 266MHz?  

 

Should I treat the EMIF as if it belongs to a different clock domain and use clock domain crossing techniques? Is it possible to run the DRAM at a lower memory clock frequency? Or is there a better solution? 

 

I would really appreciate the help
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
78 Views

Hi, 

 

 

--- Quote Start ---  

My question is as follows: What is the best practice if I want to operate my FPGA design at a different frequency than 266MHz? 

--- Quote End ---  

 

Based on datasheet parameters select frequency and use PLL also take care of Timing closer. 

 

--- Quote Start ---  

Should I treat the EMIF as if it belongs to a different clock domain and use clock domain crossing techniques? Is it possible to run the DRAM at a lower memory clock frequency? Or is there a better solution? 

--- Quote End ---  

 

Yes can use, Subjected to the datasheet, But Certain frequencies of operation give you the best possible latency based on the memory parameters, You can check the specification of DDR3 and select the frequency required for optimal performance.  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
78 Views

 

--- Quote Start ---  

Hi, 

 

 

Based on datasheet parameters select frequency and use PLL also take care of Timing closer. 

 

Yes can use, Subjected to the datasheet, But Certain frequencies of operation give you the best possible latency based on the memory parameters, You can check the specification of DDR3 and select the frequency required for optimal performance.  

 

 

--- Quote End ---  

 

 

Thanks for the response. I will consult the datasheet to see if I can use a lower memory CLK frequency.  

 

Other than this approach, is there any other techniques that are commonly used?
Altera_Forum
Honored Contributor II
78 Views

Hi, 

 

Are you concern about data processing? 

If so you can use ping pong method to access memory. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
78 Views

 

--- Quote Start ---  

 

In particular, the parameters "Memory Clock frequency" is set to 1066.66MHz and the "Clock rate of user logic" is set to quarter rate. I believe this signifies that the EMIF provides an "user clock" of frequency 266MHz, which I am meant to use to clock my design. 

 

--- Quote End ---  

 

 

Is that mean I have to connect a 266MHz clock from pin assignment? 

what if my chip don't have 266MHz clock? If I only have pll_ref_clk 150MHz 

 

and, what's different between General->Memory Clock frequency->1066.66MHz and Mem_Timing->Speed bin-> -2133 ?
Reply