FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

TSE mdc/mdio wirte/read problem.

SGDMA dropping two bytes just before (not at) end of transfer

sine wave: how to set amplitude?

How to generate a design in verilog with DSP Builder and Simulink

sin waveform simulation result

Memory read in PCIe end point design example

DSP builder blocks

HDL import blocks, Simulink signal routing, and Altera port types

ddr2 write/read problem

SerialLite configuration

Representation

Transfer function

Change wronghorizon's FFT design

Sin waveform correct?

altsyncram simulation - X output?

Featured Content

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)