FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5748 Discussions

How to activate loopback mode for debugging Cyclone V GX PCIe link

SSmit7
Novice
259 Views

Hello

I am using the PCIe-to-Avalon-MM Hard IP core in a 5CGXFC3B6U19I7 device, and I would like to enable loopback mode to debug the link between the FPGA and the processor that I am using. The FPGA is in Native endpoint mode. Can someone point me in the right direction as to how to enable loopback mode?

Thank you in advance.

Regards

0 Kudos
1 Solution
SengKok_L_Intel
Moderator
252 Views

Hi,


To achieve the loopback mode at the endpoint, the host may act as a loopback master, and send two consecutive TS1s with loopback bit set, so that the endpoint can enter the loopback mode. You may refer to the PCIe spec for the detailed information.


Regards -SK


View solution in original post

2 Replies
SengKok_L_Intel
Moderator
253 Views

Hi,


To achieve the loopback mode at the endpoint, the host may act as a loopback master, and send two consecutive TS1s with loopback bit set, so that the endpoint can enter the loopback mode. You may refer to the PCIe spec for the detailed information.


Regards -SK


View solution in original post

SengKok_L_Intel
Moderator
221 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Reply