FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

How to add BFM design file in project containg IP core

Altera_Forum
Honored Contributor II
1,139 Views

Hi, 

 

 

I am new to Quartus II tool.  

 

I have generated PCIe Hard IP (Arria II GX) simulation model with the help of MegaWizard Plug-In Manager flow in Quartus II 9.1 version. I followed the steps given in chp 2 of PCI Express Compiler User Guide.  

 

Tool has generated .qip file successfully. But While adding it to current project, it only shows files related to PCIe IP core. It is not adding files related to Chaining DMA (BFM) and testbench files. But in .qip file, it has reference to all files.  

 

Can you please tell me, How to add these other files for doing simualtion?
0 Kudos
0 Replies
Reply