How to add BFM design file in project containg IP core

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

How to add BFM design file in project containg IP core

951 Views

Hi,

I am new to Quartus II tool.

I have generated PCIe Hard IP (Arria II GX) simulation model with the help of MegaWizard Plug-In Manager flow in Quartus II 9.1 version. I followed the steps given in chp 2 of PCI Express Compiler User Guide.

Tool has generated .qip file successfully. But While adding it to current project, it only shows files related to PCIe IP core. It is not adding files related to Chaining DMA (BFM) and testbench files. But in .qip file, it has reference to all files.

Can you please tell me, How to add these other files for doing simualtion?

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.