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5886 Discussions

How to compile 2 PCIe instances in one project

vdpavel
New Contributor I
509 Views

Hi.

I need to use 2 PCIe controllers in one project. One of them for slow speed periphery like SPI and using Gen2x4 128bit 125MHz . Second one Gen3x8 256bit 250MHz. I create 2 qsys each with its own PCIe hip. If I use in project only any one of them - everything ok. But when I put both qsys get error. And this problem in Pro version of quartus only. FPGA Arria 10.

How can I workaround this?

Pavel

0 Kudos
9 Replies
Deshi_Intel
Moderator
495 Views

Hi Pavel,


  1. May I know which Arria 10 FPGA OPN that you used ? Have you confirmed the FPGA support 2 PCIe hard IP ?
  2. If answer is YES to question 1, then I suspect the issue could be on your top level design file connection
  • I noticed you are using bdf schematic. I strongly encourage you to switch to verilog or VHDL design for ease of usage
    • You can revisit to check your top level design file again


Thanks.


Regards,

dlim


vdpavel
New Contributor I
493 Views

Hi dlim

1. 10AX057N3F40E2SG

2. Actually I'm working on big project that in Standard version of quartus compiles well. In the past I used FPGAs that was not supported by pro version (Cyclone V). Before project was accepted I was working on quartus prime 18.1. Now we started this project oficially and updated quartus to pro version. Moving from standard to pro version is a nightmare. I didn't expect such problems at all. My recent post https://community.intel.com/t5/FPGA-Intellectual-Property/Quartus-Pro-v21-1-Synthesis-error-of-two-i... was first problem. We've solved it. Now second problem PCIe.

As a system engineer I wonder about decision of Intel removing bdf editing in pro version of quartus. Of course our projects use system verilog. But top level was always graphical. It is easy to understand the structure of project. Anyway no problem to use as a top of project verilog file. You know better what is the best.

I just simplified my project to have only 2 PCIe devices and get the same error as in my hole project. And it doesn't matter if the top level bdf or verilog. I attach screenshot of 18.1 quartus result and 21.1 pro result of the same hole project. I've tried to compile this project in quartus 20.1.1.170 - result as in 18.1 without any problem.

To understand each other I also attached test project. Idea very simple and I think is clear.  Could you please correct this project as it will be able to analysis and synthesis without erros?

Thanks in advance.

Regards,

Pavel

Deshi_Intel
Moderator
483 Views

Attached is the debug finding screenshot

Deshi_Intel
Moderator
481 Views

HI Pavel,


Thanks for sharing the PCIe debug design.


Debug finding shown later PCIe design somehow overwrite top PCIe design causing synthesis error. All depends on the file sequence in Quartus project

  1. Scenario 1 : Quartus project file sequence with pcie_spi design at top follow by pcie_ddr at bottom
  2.    result = Quartus synthesis error complaining elaboration failure in pcie_spi 
  3. Scenario 2 : If switch Quartus project file sequence to pcie_ddr design at top follow by pcie_spi at bottom 
  4.    result = Quartus synthesis error complaining elaboration failure in pcie_ddr


screenshot explanation is attached in earlier post.


This looks like a bug, I have filed investigation report to Intel Engineering to look into issue.


Will keep you posted on the update.


Additional comment :

  1. Side note : You may want to comment out unnecessary PCIe internal signals to avoid end up pulling few hundred over signals to your top level design file - signal port declaration. This will overwhelm Quartus fitter compilation later
  2. Unfortunately Quartus Standard and Quartus Pro each has different IP design file structure so they are not compatible to each another. You need to pick one for your design development
  3. Schematic design is not preferred anymore as FPGA design getting more complicated. It's hard to create/modify schematic design with few hundred design connection. If you like block diagram view, you can always use the "RTL viewer" feature in Quartus to generate block diagram view of your design


Thanks.


Regards,

dlim



vdpavel
New Contributor I
477 Views

Hi dlim,

Thank you for your cooperation and comments. Waiting for official investigation results.

Regards,

Pavel

Deshi_Intel
Moderator
445 Views

Hi Pavel,


Intel engineering team is still debugging the issue.


As a workaround, would you be able to use older Quartus version like v20.3 Pro for your project development while Intel continue to work on the fix for v21.1 ?

  • We found out older Quartus version is not impacted by this issue and it only affect v21.1


Thanks.


Regards,

dlim


vdpavel
New Contributor I
403 Views

Hi dlim,

Checked v20.3 is really not impacted by this issue.

Working on version 20.3 and waiting for new one.

Thanks.

Regards,

Pavel

Deshi_Intel
Moderator
396 Views

HI Pavel,


The fix will only be available in future Quartus release version which is few months in the road.


For now, appreciate if you can use v20.3 to continue with your project development first.


Thanks.


Regards,

dlim


vdpavel
New Contributor I
226 Views

Hi. Quartus pro 21.2 now works. Thank you.

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