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Altera_Forum
Honored Contributor I
968 Views

How to configure MSI interrupt

Hi, 

 

For PCIe Hard IP, how to setup/configure MSI interrupts? 

For example, I have DMA read and DMA write transactions, setting up through descriptors. At the last PTR, it sends MSI interrupts. How to configure the MSI so that the DMA read and write receive different message IDs or call different ISRs ? 

 

Thanks, 

 

Tiger
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5 Replies
Altera_Forum
Honored Contributor I
87 Views

The multiple MSI input signals will eventually OR to become a single MSI interrupt. 

It can't be configure to different message IDs.
Altera_Forum
Honored Contributor I
87 Views

Thank you for your reply. 

There are up to 16 lines of interrupt signals OR-ed into a single MSI interrupt. How these IRQ lines are associated with particular PCIe link/function or operations? e.g. Is there a way to associated DMA read completion to line A, and DMA write completion to line B? 

The message ID in the ISR routine represents something or it is just a dummy parameter?
Altera_Forum
Honored Contributor I
87 Views

For the Av-ST version at least, the message ID in the ISR routine (I'm assuming you are using KMDF/Windows) is directly related to which number the MSI is. When an MSI is send through the streaming core you also have to configure which number it is by a separate input. 

 

As for the Av-MM DMA version, I am not sure how this is done (or if it is possible).
Altera_Forum
Honored Contributor I
87 Views

Thank you.

Altera_Forum
Honored Contributor I
87 Views

You need to read *Avalon-MM to PCI Express Interrupt Status Register* to figure out who caused the interrupt. 

Normally the root port driver needs to read the Interrupt Status Register port AVL_IRQ_ASSERTED[15:0] at (CRA+0x40) to know which IRQ was active, 

each AVL_IRQ_ASSERTED[] bit reflects the value on the corresponding IRQ input port. 

Value 0 means Avalon-MM IRQ is not being signaled, value 1 means Avalon-MM IRQ is being signaled.
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