How to connect Intel LDPC IP core encoder and decoder in WiMedia 1.5 mode ?

[GKash]

provide sample connections (with one specific configuration), interconnect specifications needed

[CheePin_C_Intel]

Hi Gautam, As I understand it, you have some inquiries related to LDPC IP. Just would like to check with you which specific Quartus and device that you are using? Thank you.

[GKash]

I am using Quartus Prime Standard Edition16.0, altera_ldpc 16.0 and Cyclone V Soc Development Kit.

[CheePin_C_Intel]

Hi Gautam, As I understand it, you have some inquiries related to connecting the CV LDPC encoder to decoder in WiMedia 1.5 mode. For your information, the output of encoder will need to undergo some conversion prior to feeding into the LDPC decoder. You are unable to directly feed the output of encoder back into the decoder. You will need to perform LLR and soft bit conversion on the output data of encoder. Let me try to explain further on the meaning of LLR and soft bits as following: 1.The LLR is referring the simultaneous processing of how many bits or in other words to speed up the process. In other words, you would need to de-serialized the encoder output by factor of 2. 2.As for the soft bits, you would require to do the conversion to strongest soft bits. An example of conversion can looks like following: a.For every encoded output bit 0, convert it to 4’b0111 b.For every encoded output bit 1, convert it to 4’b1000 You can try to generate the simulation example from LDPC IP for decoder. Then you can check on the raw data fed into the decoder IP to get further insight on the conversion. Please let me know if there is any concern. Thank you.

[GKash]

Hi cpchan I understood your second point (converting into soft bits) but can u please explain what is deserializing by factor of 2. Does it mean to convert data into two liness one having odd bit and other one even. And if so is the case then which one to put in MSB side of encoder inputs. Thanks and regards Gautam

[CheePin_C_Intel]

Hi Gautam, Regarding the deserializing, yes, you are right. You will be converting the output data from encoder into two parallel bits (if LLR = 2). The first output data from encoder will be at the LSB input to decoder and second output data from encoder will be at MSB input to decoder. Then continue to alternate for the subsequent encoder output data. You may try to generate the simulation example for encoder and decoder separately. Then perform some comparison on the data in and out to have further insight. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[gkash2]

Hi CPChan

I was able to get the output from ldpc decoder as you said in previous replies.

But there are some questions and issues which i am not able to resolve.

Q1. Signal Line(decoder)named as "ldpc_decoder_in_ready" remains throughout HIGH during the procedure of feeding data to decoder. Does it mean there 's something wrong in my design? This doesn't happen with ldpc encoder. It goes low for sometime after feeding encoder data.

Issue: The output which i am getting from LDPC decoder doesn't come at uniform intervals, because of which there's a lead/lag in final output stream and i am not able to get seamless data stream(I am feeding video output from digital camera to LDPC encoder).

PS: Now i have company Email Id(gautamkashyap@deal.drdo.in) and i need help to upgrade it to Intel Premier support.

Thanks and regards

Gautam Kashyap

[CheePin_C_Intel]

Hi,

Sorry for the delay. Regarding the decoder in_ready output, if I understand you correctly, you are referring to this output remains high. For your information, the in_ready is a back-pressure output signal to the source. When the decoder FIFO is almost full, it will de-assert the in_ready to tell the source to stop the data flow.

Regarding the Intel Premier Support, it would be great if you could further engage with your local sales or FAE to further assist you on the account creation.

Please let me know if there is any concern. Thank you.

Chee Pin

[gautam_drdo]

Hi CP Chan,

With your help I was able to proceed further and integrate LDPC IP core in my system. Now the issue which I am facing is that I get errors in Decoded output. Errors occurs in a specific pattern.  Pattern is ,mainly starting bits of two adjacent blocks(600/1200 bits fed to ldpc decoder) . Errors occurs rarely, maybe 2 in 100 blocks or so, and I am not able to find the exact reason for it. Data fed to LDPC decoder is same in every block.

Since I have not been able to fully understand exact relation between parameters(number of iterations/parallelism/width of decoder variables/MSA attn. factor) in LDPC decoder, so I tried and experimented. And found that with MSA attenuation factor as 0.25, I get best output with very less errors.

Now, please help me in understanding that why my decoded output is varying rarely. And what is the inter-relation of parameters (number of iterations/parallelism/width of decoder variables/MSA attn. factor) on decoder output?

Info about my project: Quartus Prime Lite Edition 20.1 , Cyclone V ,LDPC(WiMedia 1.5, 600/1200, half rate, itr-50, Par-3, Width-4, MSA AF-0.25) Max input data rate of 16Mbps, Processing frequency is 50Mhz, (1 as 1000 and 0 as 0111, best case).

Enclosed: screenshot of error, error occurs in this pattern only.

Thanks and regards

Gautam