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In our system Intel 256P30 flash is connected with FPGA.
We want to be able to program flash. On this purpose SOPC builder design with CFI controller core was created. Then SOPC builder generated system with Avalon-like interface, but Intel P30 flash have different interface (with write enable signal, output enable signal and etc). Then question arises: How to connect flash to CFI controller? (more precisely: Should readenable_n be connected to OE_N, writeenable_n to WE_N, chipselect_n to CE_N?) And if my supposition is correct, how write operation should be performed? (Flash should recieve speсial command to perform write operation)Link Copied
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the cfi controller is just an interface between the avalon switch fabric and ypur external cfi via tri state bridge.
your are correct, you need to connect these signals as you mentioned. please pay attention about the adress lines depending on data bus width and how the manufacture of the cfi flash numbers the adr. lines. if your want to write to the cfi flash you can use the altera HAL or you need to follow the cfi flash datasheet how to "open" the cfi flash to write to specific memory blocks /areas. as this is not a ram device where you can randomly read modify write the content you need to follow the cfi program algorithm.
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