How to construct the full synchronous Video clock in and video clock out by VIP?

[Altera_Forum]

Dear Friends, 

  I want to construct the video stream by VIP suite: video clock in --> frame buffer-->video clock out. But frames must not been dropped and repeated.   I have tried to set the video clock in and video clock out IP with "video in and out use the same clock ", and frame buffer IP with "no dropping frame" and "no repetition frame", but still no work correctly.  Would you please give me some advices for this issue?  Thanks sopc

[Altera_Forum]

What you are trying to do is possible with VIP. I would try to build your system in stages. 

 First, try creating a system that uses only the Pattern Generator and the Clocked Video Output. Once that is working, replace the Pattern Generator with the Clocked Video Input. Once you have that working, add the Frame Buffer.  You probably don't want to use the "video in and out use the same clock" option. The "out" in this option is referring to the avalon streaming output of the Clocked Video Input, not the final output of the VIP chain. Typically, the avalon streaming clock would be different and faster than the source video clock.

[Altera_Forum]

I did a system like this. You cannot get output if your clocked_video_input module is directly connected with clocked_video_output. There has to be some other block in between. Just put a scaler block between video_in and video_out block and keep the output resolution of scaler to input the resolution (scaling factor of 1). To make things simpler, using nearest neighbor algorithm. I did it and it works ok.

[Altera_Forum]

Hi Faisal, 

 Quote:  you cannot get output if your clocked_video_input module is directly connected with clocked_video_output. just put a scaler block between video_in and video_out block and keep the output resolution of scaler to input the resolution (scaling factor of 1).  That the system requires a scaler with a 1:1 ratio to work makes no sense. The only way that this would change your system is by affecting the signal propagation around the FPGA, and adding some latency (not buffering.) I think that you have a timing issue that you can fix with TimeQuest.  Quote:  you cannot get output if your clocked_video_input module is directly connected with clocked_video_output.   This should (has for me) work if  a) the output clock is equal to or derived from the input clock, and  b) the resolutions are the same This will give the same frame rate. Frame rate is critical as the differences in the frame ultimately determine your buffering requirements and the under/over flow performance in your system.