Hello,
I'm trying to do the loop test of Rapidio.
I genereated test data on io_s_wr_writedata, connected the td and rd signals, and I generated the io_s_rd signals in order to receive the data.
But there is no data received on io slave receive data bus io_s_rd_readdata.
According to simulation on ModelSim, there is a io_s_rd_readerror generating accompaning with io_s_rd_readdatavalid.
I looked up the ug and I found the following tip:
The io_s_rd_readerror output is asserted when a response with ERROR status is received for an NREAD request packet, when an NREAD request times out, or when the Avalon-MM address falls outside of the enabled address mapping window. As required by the Avalon-MM interface specification, a burst in which the io_s_rd_readerror signal is asserted completes despite the error signal assertion.
I'd like to know to deal with the problem.
I have set the Input/Output Slave Mapping Window n mask register and Input/Output Slave Mapping Window n Control register.
http://www.alteraforum.com/forum/attachment.php?attachmentid=12391&stc=1
