FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

How to define the NULL descriptor in SGDMA

Altera_Forum
Honored Contributor II
1,966 Views

I use the SGDMA in TSE MAC. 

As its document said, the last descriptor in the descriptor chain must be a 

NULL descriptor. But I wonder how to define the NULL descriptor. 

I define it in following way: 

/***************************************************/ 

alt_sgdma_descriptor* tx_descriptor = (alt_sgdma_descriptor*)DESCRIPTOR_MEN_BASE; 

 

alt_sgdma_descriptor* tx_descriptor_ = (alt_sgdma_descriptor*)(DESCRIPTOR_MEN_BASE + ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE); 

 

alt_avalon_sgdma_construct_mem_to_stream_desc(tx_descriptor, tx_descriptor_, read_buffer, 256, 0, 1, 1, 0); 

 

alt_avalon_sgdma_construct_mem_to_stream_desc(tx_descriptor_, (alt_sgdma_descriptor*)NULL, read_buffer, 256, 0, 1, 1, 0); 

/****************************************************/ 

where tx_descriptor is the first descriptor, and tx_descriptor_ is the second(also the last descriptor) descriptor,. 

I define the NULL descriptor use (alt_sgdma_descriptor*)NULL 

Is that right?
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
808 Views

I also had this question, and I am not sure what is the correct answer. 

 

 

I *think* that a null descriptor is the (last) descriptor with the OWNED_BY_HARDWARE bit set. It's addresses and length are "don't cares". 

 

I think the SG DMA engine will stop upon reaching this descriptor. 

 

The documentation is not quite clear on this. 

 

Regards, 

 

Leon.
0 Kudos
Altera_Forum
Honored Contributor II
808 Views

your right leon

0 Kudos
Altera_Forum
Honored Contributor II
808 Views

Correction: 

- the null descriptor is the last descriptor with the OWNED_BY_HARDWARE bit _cleared_. (not set as I typed earlier). 

 

Addition: 

- the null descriptor addresses and length are "don't cares", as the SG DMA engine will not perform a DMA transfer for this last descriptor. 

 

Can someone comment if this is correct or not??
0 Kudos
Altera_Forum
Honored Contributor II
808 Views

likewise : That is correct and the alt_avalon_sgdma_construct_* macros takes care of this.  

It always sets the "next" descriptor to NULL.
0 Kudos
Reply