Hi, I'm trying to find an example on how to accomplish frame rate conversion with VIP cores. Does anyone have such example?For example, what would be the correct way of doing a simple scaling function that takes in 1080p@60 and outputs 720p@60 ? I understand that scaler-ip block would process the image to correct size (from 1920x1080 to 1280x720 but at 120Hz?) but how can I reduce the clock rate from 148.5MHz to 74.25MHz without overflowing the input entirely? I'm sure I'm missing something fundamental in these VIP blocks. Perhaps its just to run different clocks into the "Clocked video input" and "clocked video output". Is it that simple? Or is Frame buffer required and if so, does that need to be controlled with Nios? Thank you.
The simplest way to do a frame rate conversion with VIP is to use the frame buffer in tripple buffer mode with frame repeat/dropping enabled.When scaling from 1080p60 to 720p60, you don't actually need to do a frame rate conversion assuming the input and output frame rates are locked to each other. For example, you can use a PLL to divide down the 148.5 MHz clock to 74.25 MHz which you can feed to the clocked video output. One thing to look out for is that the frame rates really are the same. For example, 720x480p with a 27 MHz clock is actually 59.94 frames a second, not 60.
Hi KevinI am trying to develop a frame synchronizer here which shares some of the principles of frame rate conversion. Do you know what should be done with audio packets when there is a frame dropping/repeating? Thank you! Best regards, Thiago
Thanks Kevin,I will try the frame locking. Also, what would be the most efficient clock for the scaler block in this case? Could it be from the incoming 148.5 as well or is it better to decouple and use a fixed clock from an unrelated PLL (or from the sysclk that the frame buffer generates) as long as it's greater than 148.5.
What you are doing is not actually frame rate conversion. You are doing a downconversion but your frame rates are the same. What are the physical interfaces for your video (SDI, HDMI, etc.)Are you aware that Altera has a UDX reference design? http://www.altera.com/support/refdesigns/sys-sol/broadcast/ref-format-conversion-udx3.html Jake
Hi Jake,Input is DVI 24bits and separate HS/VS. The goal is to up and downconvert between 1080p and 720p. So you are right, the frame rate shouldn't change but it would seem to me that the clock frequency must toggle between 74.25 and 148.5 - I don't know if this manifests itself as 60/120Hz frame rate that should be converted. Thanks for the UDX info.
If all you want to do is scale 1080p60 to 720p60, you should be able to do it with the following three VIP blocks:CVI -> Scaler -> CVO All three of these should use the same clock for their Avalon streaming interface. This clock would generally be faster than your fastest pixel clock, but you can get away with a little less as once you take into account the horizontal blanking, the average rate is actually less than the pixel clock. The CVI also needs a clock for it's video input. This would be the 148.5 MHz clock from your DVI receiver. The CVO needs a clock for it's video output. You can use a PLL to divide the 148.5 MHz input clock to 74.25 MHz for this purpose. There is no frame rate issue to worry about. The scaler will just output data at half the rate of it's input. The scalers Avalon streaming output will just be idle more than half the time.