How to generate 128-bit DDR3 interface on Cyclone 10 GX

[DKron4]

I'm trying to implement a 128-bit DDR3 interface in a Cylone 10 GX 10CX105. I have made a design to test this, but cannot get successful placement. Is there a reference example of how to configure such an interface? According to "Intel Cyclone 10 GX EMIF IP Product Architecture" (UG-20116), DDR3 interfaces up to 144 bit are supported.

My ultimate goal is to get 4 DDR3 SODIMM modules connected to 1 FPGA for a total of 64GB of memory. The ping pong interface seems to allow an interface this wide, but I need 8 chip selects, and only 4 are allowed. With two 64-bit interfaces, I can't get successful placement. Is there any way to achieve this?

[sstrell]

Interfaces may be supported that wide but the device you've selected may not be large enough to accommodate what you want. Things to try:

Create an example design. Configure the IP the way you want and then generate the example design on the tab in the IP Parameter Editor. See this training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html

Use Interface Planner. After generating an example design or generating just the interface to connect to your user logic, synthesize and use Interface Planner to see what your options are for placement in the device. See this training for details:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oblueintro.html

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