FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6020 Discussions

How to generate MSIx interrupts in AvalonMM Startix10 PCIe HardIP+ when configured it as end point. And there are no signals like tl_cfg_ctl,tl_cfg_add,tl_cfg_func,MSIx_intfc_o which are available in other PCIe IPs of startix 10 why?

Nagaraju
Beginner
342 Views
 
0 Kudos
4 Replies
SengKok_L_Intel
Moderator
281 Views

Hi,

 

For AVMM Stratix 10 PCIe Hard IP+, the MSI/MSI-X interface needs access via tl_cfg, but this interface is now not available at the top level. However, you can still find this interface at a lower layer instance which is "intel_pcie_s10_avmm_bridge_512.sv". I will feedback this to the Intel PSG engineering team to export those signals to the top level so that the user can access it directly without any manual modification.

 

Regards -SK

SengKok_L_Intel
Moderator
277 Views

Just for your information, the Intel PSG engineering team is in progress to enhance the IP to address this concern in the future IP release. 

Regards -SK  

Nagaraju
Beginner
246 Views

Not on Avalon MM Interface, how I can read the MSIx Capability registers and TPH capability Registers. Beacuse they need to be used in my RTL.

SengKok_L_Intel
Moderator
268 Views

This problem is planned to fix in the next Quartus release version, where the tl_cfg interface will be exported by default from the IP at the top layer.


If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


Regards -SK


Reply