For AVMM Stratix 10 PCIe Hard IP+, the MSI/MSI-X interface needs access via tl_cfg, but this interface is now not available at the top level. However, you can still find this interface at a lower layer instance which is "intel_pcie_s10_avmm_bridge_512.sv". I will feedback this to the Intel PSG engineering team to export those signals to the top level so that the user can access it directly without any manual modification.
This problem is planned to fix in the next Quartus release version, where the tl_cfg interface will be exported by default from the IP at the top layer.
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