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Hi,
For AVMM Stratix 10 PCIe Hard IP+, the MSI/MSI-X interface needs access via tl_cfg, but this interface is now not available at the top level. However, you can still find this interface at a lower layer instance which is "intel_pcie_s10_avmm_bridge_512.sv". I will feedback this to the Intel PSG engineering team to export those signals to the top level so that the user can access it directly without any manual modification.
Regards -SK
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Just for your information, the Intel PSG engineering team is in progress to enhance the IP to address this concern in the future IP release.
Regards -SK
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Not on Avalon MM Interface, how I can read the MSIx Capability registers and TPH capability Registers. Beacuse they need to be used in my RTL.
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This problem is planned to fix in the next Quartus release version, where the tl_cfg interface will be exported by default from the IP at the top layer.
If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards -SK
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