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Novice
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Warning of timing analysis of UniPHY IP

Intel IP was used and automated generated SDC file was used.

Should I do any action on these warnings from timing analysis?

 

PLL clock mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL, and not go through a global clock network. Timing analyses may not be valid.

Ignored create_clock at nios_mem_if_ddr2_emif_0_p0.sdc(225): Incorrect assignment for clock. Source node: clock_pll_0_in_clk_clk already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.

 

No paths exist between clock target "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[4]" of clock "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[4]_afi_clk" and its clock source. Assuming zero source clock latency.

No paths exist between clock target "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[1]" of clock "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[1]_dq_write_clk" and its clock source. Assuming zero source clock latency.

No paths exist between clock target "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0]" of clock "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0]_write_clk" and its clock source. Assuming zero source clock latency.

No paths exist between clock target "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[2]" of clock "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[2]_resync_clk" and its clock source. Assuming zero source clock latency.

No paths exist between clock target "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[3]" of clock "mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[3]_tracking_clk" and its clock source. Assuming zero source clock latency.

 

   Clock: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0]_write_clk with master clock period: 40.000 found on PLL node: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0] does not match the master clock period requirement: 13.333

   Clock: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[1]_dq_write_clk with master clock period: 40.000 found on PLL node: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[1] does not match the master clock period requirement: 13.333

   Clock: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[2]_resync_clk with master clock period: 40.000 found on PLL node: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[2] does not match the master clock period requirement: 13.333

   Clock: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[3]_tracking_clk with master clock period: 40.000 found on PLL node: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[3] does not match the master clock period requirement: 13.333

   Clock: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[4]_afi_clk with master clock period: 40.000 found on PLL node: mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[4] does not match the master clock period requirement: 13.333

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Novice
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Re: Warning of timing analysis of UniPHY IP

one more:

PLL clock mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL, and not go through a global clock network. Timing analyses may not be valid.

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Highlighted
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Re: Warning of timing analysis of UniPHY IP

Hi,

You may refer to the KDB: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

It is recommended that you use a dedicated clock input pin that is directly routed to the memory controller reference clock input.

Thanks

Best regards,

KhaiY

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Highlighted
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Re: Warning of timing analysis of UniPHY IP

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY

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