I'm used to the Xilinx XPM libraries, they automatically add all the necessary constraints.
I'm trying to use DCFIFO but I really struggle.
First, I read embedded constraints are automatically added when dcfifo is used.
- https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/embedded-timing-constraint.html shows my instances
- shows the instances HAVE to contain dcfifo...
- Why aren't they scoped to all dcfifo's instances regardless of their name?
I then renamed all my instances with dcfifo.
A compilation later, I still see lots of CDC timings, among others:
FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g~DUPLICATE FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g~DUPLICATE FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb~RTM_6
Why do I get these timings? Why aren't they automatically constrained?
I also get CDC timings on the reset paths even though I set both parameters read_aclr_synch and write_aclr_synch to "ON" and the reset is synchronous to the write clock. I've also tried read_aclk_synch=OFF and write_aclk_synch=ON.
dcfifo #( .intended_device_family ("Agilex"), .lpm_numwords (512), .lpm_showahead ("ON"), .lpm_type ( "dcfifo"), .lpm_width (576), .lpm_widthu (10), .add_usedw_msb_bit ("ON"), .read_aclr_synch ("ON"), .write_aclr_synch ("ON"), .rdsync_delaypipe (2), .wrsync_delaypipe (2) ) usr_dcfifo_i ( .aclr (s_app_reset), .wrclk (s_app_clk), .wrfull (usr_fifo.wr_full), .wrreq (usr_fifo.wr_en), .data (usr_fifo.wr_data), .wrusedw (usr_fifo.wr_data_count), .rdclk (m_axi_clk), .rdempty (usr_fifo.rd_empty), .rdreq (usr_fifo.rd_en), .q (usr_fifo.rd_data), .rdusedw (usr_fifo.rd_data_count), .eccstatus (), .rdfull (), .wrempty () );
According to DCFIFO Timing Constraint Setting in the link below, FIFO parameter editor provides the timing constraint setting for the DCFIFO function. A user configurable SDC file is generated automatically when DCFIFO is instantiated from the IP Catalog. New timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay are used to constraint the design properly.
I don't use the IP Catalog and I don't generate an IP, I directly use the primitive dcfifo as shown in the OP.
We would like to avoid having to create/generate an IP for a simple fifo, unnecessary extra dependencies are unwelcome.
Also, even by using a "FIFO Intel FPGA IP", disabling "Generate SDC file and disable embedded timing constraint" gives the same timing errors.
My question is regarding the DCFIFO's embedded constraints. Some constraints are missing.
I'm not looking for a workaround, I'd like Intel to stop being incoherent and fix their primitives. There is no reason on earth a primitive needs to be constrained outside by the end-user itself.
Is that so complicated to embed all the necessary constraints into Quartus without the need to check on the forum and years old KDBs?
Xilinx is capable of it with their xpm library, why Intel can't? They have existed for years.
Feel free to close the issue once this is reported to be fixed.