How to get the FIFO informations

[Altera_Forum]

hi all , recently i modify the reference design "a2gx125_qsys_pcie_gen1x4_11_0_1"(using a dual clock onchip_fifo_memory replace the original onchip_memory,BTW,thanks to the author of this reference design )to achieve the Qsys struct “I/O -> FIFO -> mSGDMA -> PCIe -> PC memory”.now the questions are: 

1) since i don't add nios in it , how can i control the fifo indata correcttly without nios? how can i get the fifo informations such as almost_full and almost_emputy in my logic design? 2) if i complete iteam 1), i can't figure out how the PC know the my fifo is full,is it all about the pc software design , none of the FPGA's busyness ?  i don't know how the pcie chain communicate to the pc , could someone give some help or list out some refferences for me? :confused:

[Altera_Forum]

I suggest you start reading the Altera PCIe user guide: http://www.altera.com/literature/ug/ug_pci_express.pdf 

 It explains the interfaces available from the PCIe cores. You will have to write a custom component to handle the Avalon-ST or Avalon-MM interface without a Nios.  Using hard core on an ArriaII, you have to use a 64-bit Streaming interface, which means you have to pull apart the TLPs yourself. I recommend getting the mindshare PCIe system architecture book, that explains how TLPs should be generated and controlled.  http://www.mindshare.com/learn/?section=11e3067e0ba2

[Altera_Forum]

appreciate for replying,i will try that.