FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5946 Discussions

half rate memory interface design using dq_dqs2

Honored Contributor II


I am using Stratix V FPGA to implement a DDR memory intreface which takes a half rate input from the FPGA. The megafunction generation wizard for dq_dqs2 only allows the option to use half rate for output path (memory write) the read path going into the FPGA core is always full rate. How do I get the half rate in the read path as well ?
0 Kudos
0 Replies