Honored Contributor II
03-02-2012 07:52 PM
Hi,I am using Stratix V FPGA to implement a DDR memory intreface which takes a half rate input from the FPGA. The megafunction generation wizard for dq_dqs2 only allows the option to use half rate for output path (memory write) the read path going into the FPGA core is always full rate. How do I get the half rate in the read path as well ?